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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\GaoYun\work\lvds1280_800_7to1_led_screen\test_board\7001_matter\7001_unpack\project\src\led_part\SPI7001.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV55PG484C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-55</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Sep  2 15:51:35 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>SPI7001</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.113s, Peak memory usage = 57.406MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 57.406MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 57.406MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 57.406MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 57.406MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 57.406MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 57.406MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 57.406MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 57.406MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 57.406MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 57.406MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 57.406MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 88.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 88.254MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 88.254MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 88.254MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>147</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>109</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>100</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>9</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>321</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>254</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>36</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>27</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>490</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>41</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>101</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>348</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>3</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>493(493 LUT, 0 ALU) / 54720</td>
<td><1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>321 / 41997</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 41997</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>321 / 41997</td>
<td><1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 140</td>
<td>0%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clock</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>clock_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clock</td>
<td>100.000(MHz)</td>
<td>87.504(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.714</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.039</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.325</td>
</tr>
<tr>
<td class="label">From</td>
<td>DCLK_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>state_cnt_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tINS</td>
<td>FF</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>5.474</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>DCLK_s2/CLK</td>
</tr>
<tr>
<td>5.706</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>7</td>
<td>DCLK_s2/Q</td>
</tr>
<tr>
<td>6.180</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2071_s11/I3</td>
</tr>
<tr>
<td>6.551</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n2071_s11/F</td>
</tr>
<tr>
<td>7.025</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>data48_reg_47_s7/I1</td>
</tr>
<tr>
<td>7.580</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>data48_reg_47_s7/F</td>
</tr>
<tr>
<td>8.054</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2082_s18/I1</td>
</tr>
<tr>
<td>8.609</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n2082_s18/F</td>
</tr>
<tr>
<td>9.083</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2082_s16/I2</td>
</tr>
<tr>
<td>9.536</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n2082_s16/F</td>
</tr>
<tr>
<td>10.010</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2082_s14/I1</td>
</tr>
<tr>
<td>10.565</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n2082_s14/F</td>
</tr>
<tr>
<td>11.039</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>state_cnt_1_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.360</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>state_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>10.325</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>state_cnt_1_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.114</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.489, 44.726%; route: 2.844, 51.105%; tC2Q: 0.232, 4.169%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.676</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.001</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.325</td>
</tr>
<tr>
<td class="label">From</td>
<td>DCLK_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>state_cnt_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tINS</td>
<td>FF</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>5.474</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>DCLK_s2/CLK</td>
</tr>
<tr>
<td>5.706</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>7</td>
<td>DCLK_s2/Q</td>
</tr>
<tr>
<td>6.180</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2071_s11/I3</td>
</tr>
<tr>
<td>6.551</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n2071_s11/F</td>
</tr>
<tr>
<td>7.025</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>data48_reg_47_s7/I1</td>
</tr>
<tr>
<td>7.580</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>data48_reg_47_s7/F</td>
</tr>
<tr>
<td>8.054</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2082_s18/I1</td>
</tr>
<tr>
<td>8.609</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n2082_s18/F</td>
</tr>
<tr>
<td>9.083</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2082_s16/I2</td>
</tr>
<tr>
<td>9.536</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n2082_s16/F</td>
</tr>
<tr>
<td>10.010</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2083_s14/I0</td>
</tr>
<tr>
<td>10.527</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n2083_s14/F</td>
</tr>
<tr>
<td>11.001</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>state_cnt_0_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.360</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>state_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>10.325</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>state_cnt_0_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.114</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.451, 44.346%; route: 2.844, 51.456%; tC2Q: 0.232, 4.198%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.556</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.881</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.325</td>
</tr>
<tr>
<td class="label">From</td>
<td>DCLK_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>state_s_id_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tINS</td>
<td>FF</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>5.474</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>DCLK_s2/CLK</td>
</tr>
<tr>
<td>5.706</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>7</td>
<td>DCLK_s2/Q</td>
</tr>
<tr>
<td>6.180</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2071_s11/I3</td>
</tr>
<tr>
<td>6.551</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n2071_s11/F</td>
</tr>
<tr>
<td>7.025</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>data48_reg_47_s7/I1</td>
</tr>
<tr>
<td>7.580</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>data48_reg_47_s7/F</td>
</tr>
<tr>
<td>8.054</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2072_s18/I0</td>
</tr>
<tr>
<td>8.571</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n2072_s18/F</td>
</tr>
<tr>
<td>9.045</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2075_s15/I0</td>
</tr>
<tr>
<td>9.562</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n2075_s15/F</td>
</tr>
<tr>
<td>10.036</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2075_s12/I3</td>
</tr>
<tr>
<td>10.407</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n2075_s12/F</td>
</tr>
<tr>
<td>10.881</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>state_s_id_0_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.360</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>state_s_id_0_s1/CLK</td>
</tr>
<tr>
<td>10.325</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>state_s_id_0_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.114</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.331, 43.111%; route: 2.844, 52.598%; tC2Q: 0.232, 4.291%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.289</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.036</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.325</td>
</tr>
<tr>
<td class="label">From</td>
<td>DCLK_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>state_cnt_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tINS</td>
<td>FF</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>5.474</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>DCLK_s2/CLK</td>
</tr>
<tr>
<td>5.706</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>7</td>
<td>DCLK_s2/Q</td>
</tr>
<tr>
<td>6.180</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2071_s11/I3</td>
</tr>
<tr>
<td>6.551</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n2071_s11/F</td>
</tr>
<tr>
<td>7.025</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>data48_reg_47_s7/I1</td>
</tr>
<tr>
<td>7.580</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>data48_reg_47_s7/F</td>
</tr>
<tr>
<td>8.054</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2072_s18/I0</td>
</tr>
<tr>
<td>8.571</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n2072_s18/F</td>
</tr>
<tr>
<td>9.045</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2078_s14/I0</td>
</tr>
<tr>
<td>9.562</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n2078_s14/F</td>
</tr>
<tr>
<td>10.036</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>state_cnt_5_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.360</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>state_cnt_5_s1/CLK</td>
</tr>
<tr>
<td>10.325</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>state_cnt_5_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.114</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.960, 42.964%; route: 2.370, 51.951%; tC2Q: 0.232, 5.085%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.315</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.010</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.325</td>
</tr>
<tr>
<td class="label">From</td>
<td>DCLK_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>state_s_id_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tINS</td>
<td>FF</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>5.474</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>DCLK_s2/CLK</td>
</tr>
<tr>
<td>5.706</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>7</td>
<td>DCLK_s2/Q</td>
</tr>
<tr>
<td>6.180</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>data96_reg_95_s6/I1</td>
</tr>
<tr>
<td>6.735</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>data96_reg_95_s6/F</td>
</tr>
<tr>
<td>7.209</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2054_s9/I2</td>
</tr>
<tr>
<td>7.662</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>n2054_s9/F</td>
</tr>
<tr>
<td>8.136</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2074_s15/I1</td>
</tr>
<tr>
<td>8.691</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n2074_s15/F</td>
</tr>
<tr>
<td>9.165</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n2074_s12/I3</td>
</tr>
<tr>
<td>9.536</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n2074_s12/F</td>
</tr>
<tr>
<td>10.010</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>state_s_id_1_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>321</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.360</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>state_s_id_1_s1/CLK</td>
</tr>
<tr>
<td>10.325</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>state_s_id_1_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.114</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.934, 42.637%; route: 2.370, 52.248%; tC2Q: 0.232, 5.115%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 100.000%</td></tr>
</table>
<br/>
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